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?2006 silicon storage technology, inc. s71328-00-000 11/06 1 the sst logo and superflash are registered trademarks of silicon storage technology, inc. these specifications are subject to change without notice. advance information features: ? single voltage read and write operations ? 1.65-1.95v ? serial interface architecture ? spi compatible: mode 0 and mode 3 ? high speed clock frequency ?40mhz ? superior reliability ? endurance: 100,000 cycles (typical) ? greater than 100 years data retention ? ultra-low power consumption: ? active read current: 9 ma (typical @ 20mhz) ? standby current: 2 a (typical) ? flexible erase capability ? uniform 4 kbyte sectors ? uniform 32 kbyte overlay blocks ? uniform 64 kbyte overlay blocks (2 mbit only) ? fast erase and byte-program: ? chip-erase time: 125 ms (typical) ? sector-/block-erase time: 62ms (typical) ? byte-program time: 50 s (typical) ? auto address increment (aai) programming ? decrease total chip programming time over byte_program operations ? end-of-write detection ? software polling the busy bit in status register ? busy status readout on so pin ? reset pin (rst#) or programmable hold pin (hold#) option ? hardware reset pin as default ? hold pin option to suspend a serial sequence without deselecting the device ? write protection (wp#) ? enables/disables the lock-down function of the status register ? software write protection ? write protection through block-protection bits in status register ? temperature range ? commercial: 0c to +70c ? industrial: -40c to +85c ? packages available ? 8-lead soic (150 mils) ? all non-pb (lead-free) devices are rohs compliant product description the sst25wf512/010/020 are members of the serial flash 25 series family and features a four-wire, spi-com- patible interface that allows for a low pin-count package which occupies less board space and ultimately lowers total system costs. sst25wf512/010/020 spi serial flash memories are manufactured with sst proprietary, high- performance cmos superflash technology. the split-gate cell design and thick-oxide tunneling injector attain better reliability and manufacturability compared with alternate approaches. the sst25wf512/010/020 devices significantly improve performance and reliability, while lowering power consump- tion. the devices write (program or erase) with a single power supply of 1.65-1.95v for sst25wf512/010/020. the total energy consumed is a function of the applied volt- age, current, and time of application. since for any given voltage range, the superflash technology uses less cur- rent to program and has a shorter erase time, the total energy consumed during any erase or program operation is less than alternative flash memory technologies. the sst25wf512/010/020 devices are offered in an 8- lead, 150 mils soic package. see figure 2 for the pin assignment. 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 sst25vf016b16mb serial peripheral interface (spi) flash memory
2 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 figure 1: functional block diagram 1328 f01.0 i/o buffers and data latches superflash memory x - decoder control logic address buffers and latches ce# y - decoder sck si so wp# rst#/hold# serial interface note: so pin is an ry/by# pin when in aai mode and pin is enabled as a ready/busy status pin. see ?end-of-write detection? on page 13 for more information.
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 3 ?2006 silicon storage technology, inc. s71328-00-000 11/06 pin description figure 2: pin assignment for 8-lead soic table 1: pin description symbol pin name functions sck serial clock to provide the timing of the serial interface. commands, addresses, or input data are latc hed on the rising edge of the clock input, while output data is shifted out on the falling edge of the clock input. si serial data input to transfer commands, addresses, or data serially into the device. inputs are latched on the rising edge of the serial clock. so serial data output to transfer data serially out of the device. data is shifted out on the falling edge of the serial clock. the so pin is an ry/by# pin when in aai mode and the pin is enabled as a ready/ busy status pin. see ?end-of-write dete ction? on page 13 for more information. ce# chip enable the device is enabled by a high to lo w transition on ce#. ce# must remain low for the duration of any command sequence. wp# write protect the write protect (wp#) pin is used to enable/disable bpl bit in the status register. rst#/hold# reset to reset the operation of the device and the internal logic. the device powers on with rst# pin functionality as default. hold to temporarily stop serial communication with spi flash memory while device is selected. this is selected by an instruction sequence which is detailed in reset/hold mode section on page 10. v dd power supply to provide power supply voltage: 1.65-1.95v for sst25wf512/010/020 v ss ground t1.0 1328 1 2 3 4 8 7 6 5 ce# so wp# v ss v dd rst#/hold# sck si top view 1328.25wf 08-soic-p0.0
4 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 memory organization the sst25wf512/010/020 s uperflash memory arrays are organized in uniform 4 kbyte with 16 kbyte, 32 kbyte, and 64 kbyte (2mbit only) overlay erasable blocks. device operation the sst25wf512/010/020 are accessed through the spi (serial peripheral interface) bus compatible protocol. the spi bus consist of four control lines; chip enable (ce#) is used to select the device, and data is accessed through the serial data input (si), serial data output (so), and serial clock (sck). the sst25wf512/010/020 support both mode 0 (0,0) and mode 3 (1,1) of spi bus operations. the difference between the two modes, as shown in figure 3, is the state of the sck signal when the bus master is in stand-by mode and no data is being transferred. the sck signal is low for mode 0 and sck signal is high for mode 3. for both modes, the serial data in (si) is sampled at the rising edge of the sck clock signal and the serial data output (so) is driven after the falling edge of the sck clock signal. figure 3: spi protocol 1328 f03.0 mode 3 sck si so ce# mode 3 don't care bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 mode 0 mode 0 high impedance msb msb
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 5 ?2006 silicon storage technology, inc. s71328-00-000 11/06 reset/hold mode the rst#/hold# pin provides either a hardware reset or a hold pin. from power-on, the rst#/hold# pin defaults as a hardware reset pin (rst#). the hold mode for this pin is a user selected option where an enable-hold instruction is initiated to enter the hold mode. once selected as a hold pin (hold#), the rst#/hold# pin will be configured as a hold# pin, and goes back to rst# pin only after a power- off and power-on sequence. reset if the rst#/hold# pin is used as a reset pin, rst# pin provides a hardware method for resetting the device. driv- ing the rst# pin high puts the device in normal operating mode. the rst# pin must be driven low for a minimum of t rst time to reset the device. the so pin is in high imped- ance state while the device is in reset. a successful reset will reset the status register to its power-up state. see fig- ure 4 for default power-up modes. a device reset during an active program or erase operation aborts the operation and data of the targeted address range may be corrupted or lost due to the aborted erase or program operation. the device exits aai programming mode in progress and places the so pin in high impedance state. figure 4: reset timing diagram table 2: reset timing parameters symbol parameter min max units t rst reset pulse width 100 ns t rhz reset to high-z output 107 ns t recr reset recovery from read 100 ns t recp reset recovery from program 10 s t rece reset recovery from erase 1 ms t2.1328 1328 fx4.0 ce# so si sck rst# t recr t recp t rece t rst t rhz
6 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 hold the hold operation enables the hold pin functionality of the rst#/hold# pin. once set to hold pin mode, the rst#/ hold# pin continues functioning as a hold pin until the device is powered off and then powered on. after a power- off and power-on, the pin functionality returns to a reset pin (rst#) mode. see ?enable-hold (ehld)? on page 19 for detailed timing of the hold instruction. in the hold mode, serial sequences underway with the spi flash memory are paused without resetting the clocking sequence. to activate the hold# mode, ce# must be in active low state. the hold# mode begins when the sck active low state coincides with the falling edge of the hold# signal. the hold mode ends when the rising edge of the hold# signal coincides with the sck active low state. if the falling edge of the hold# signal does not coin- cide with the sck active low state, then the device enters hold mode when the sck next reaches the active low state. similarly, if the rising edge of the hold# signal does not coincide with the sck active low state, then the device exits in hold mode when the sck next reaches the active low state. see figure 5 for hold condition waveform. once the device enters hold mode, so will be in high- impedance state while si and sck can be v il or v ih. if ce# is driven active high during a hold condition, the device returns to standby mode. the device can then be re-initiated with the command sequences listed in tables 8 and 9. as long as hold# signal is low, the memory remains in the hold condition. to resume communication with the device, hold# must be driven active high, and ce# must be driven active low. see figure 5 for hold tim- ing. figure 5: hold condition waveform write protection sst25wf512/010/020 provide software write protection. the write protect pin (wp#) enables or disables the lock- down function of the status register. the block-protection bits (bp1, bp0, and bpl) in the status register provide write protection to the memory array and the status regis- ter. see table 5 for the block-protection description. write protect pin (wp#) the write protect (wp#) pin enables the lock-down func- tion of the bpl bit (bit 7) in the status register. when wp# is driven low, the execution of the write-status-register (wrsr) instruction is determined by the value of the bpl bit (see table 3). when wp# is high, the lock-down func- tion of the bpl bit is disabled. active hold active hold active 1328 fx5.0 sck hold# table 3: conditions to execute write-status-register (wrsr) instruction wp# bpl execute wrsr instruction l 1 not allowed l 0 allowed h x allowed t3.0 1328
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 7 ?2006 silicon storage technology, inc. s71328-00-000 11/06 status register the software status register provides status on whether the flash memory array is available for any read or write oper- ation, whether the device is write enabled, and the state of the memory write protection. during an internal erase or program operation, the status register may be read only to determine the completion of an operation in progress. table 4 describes the function of each bit in the software status register. busy the busy bit determines whether there is an internal erase or program operation in progress. a ?1? for the busy bit indi- cates the device is busy with an operation in progress. a ?0? indicates the device is ready for the next valid operation. write enable latch (wel) the write-enable-latch bit indicates the status of the inter- nal write-enable-latch memory. if the wel bit is set to ?1?, it indicates the device is write enabled. if the bit is set to ?0? (reset), it indicates the device is not write enabled and does not accept any write (program/erase) commands. the write-enable-latch bit is automatically reset under the following conditions: ? reset instruction completion ? power-up ? write-disable (wrdi) instruction completion ? byte-program instruction completion ? auto address increment (aai) programming is completed or reached its highest unprotected memory address ? sector-erase instruction completion ? block-erase instruction completion ? chip-erase instruction completion ? write-status-register instructions auto address increment (aai) the auto address increment programming-status bit pro- vides status on whether the device is in aai programming mode or byte-program mode. the default at power up is byte-program mode. table 4: software status register bit name function default at power-up read/write 0 busy 1 = internal write operation is in progress 0 = no internal write operation is in progress 0r 1 wel 1 = device is memory write enabled 0 = device is not memory write enabled 0r 2 bp0 indicate current level of block write protection (see table 5) 1 r/w 3 bp1 indicate current level of block write protection (see table 5) 1 r/w 6 aai auto address increment programming status 1 = aai programming mode 0 = byte-program mode 0r 7 bpl 1 = bp1 and bp0 are read-only bits 0 = bp1 and bp0 are read/writable 0r/w t4.0 1328
8 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 block protection (bp1, bp0) the block-protection (bp1, bp0) bits define the size of the memory area to be software protected against any mem- ory write (program or erase) operation, see table 5. the write-status-register (wrsr) instruction is used to pro- gram the bp1 and bp0 bits as long as wp# is high or the block-protect-lock (bpl) bit is ?0?. chip-erase can only be executed if block-protection bits are all ?0?. after power-up, bp1 and bp0 are set to defaults. see table 4 for defaults at power-up. block protection lock-down (bpl) when the wp# pin is driven low (v il ), it enables the block- protection-lock-down (bpl) bit. when bpl is set to ?1?, it prevents any further alteration of the bpl, bp1, and bp0 bits. when the wp# pin is driven high (v ih ), the bpl bit has no effect and its value is ?don?t care?. after power-up, the bpl bit is reset to ?0?. table 5: software status register block protection for sst25wf512 protection level status register bit protected memory address bp1 1 1. default at power-up for bp1 and bp0 is ?11?. bp0 512 mbit none 0 0 none 1 (upper quarter memory) 0 1 0c000h-0ffffh 2 (upper half memory) 1 0 08000h-0ffffh 3 (full memory) 1 1 00000h-0ffffh t5.0 1328 table 6: software status register block protection for SST25WF010 protection level status register bit protected memory address bp1 1 1. default at power-up for bp1 and bp0 is ?11?. bp0 1 mbit none 0 0 none 1 (upper quarter memory) 0 1 018000h-01ffffh 2 (upper half memory) 1 0 010000h-01ffffh 3 (full memory) 1 1 000000h-01ffffh t6.0 1328 table 7: software status register block protection for sst25wf020 protection level status register bit protected memory address bp1 1 1. default at power-up for bp1 and bp0 is ?11?. bp0 2 mbit none 0 0 none 1 (upper quarter memory) 0 1 030000h-03ffffh 2 (upper half memory) 1 0 020000h-03ffffh 3 (full memory) 1 1 000000h-03ffffh t7.0 1328
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 9 ?2006 silicon storage technology, inc. s71328-00-000 11/06 instructions instructions are used to read, write (erase and program), and configure the sst25wf512/010/020. the instruction bus cycles are 8 bits each for commands (op code), data, and addresses. prior to executing any page-program, auto address increment (aai) programming, sector-erase, block-erase, write-status-register, or chip-erase instruc- tions, the write-enable (wren) instruction must be exe- cuted first. the complete list of instructions is provided in table 8. all instructions are synchronized off a high-to-low transition of ce#. inputs will be accepted on the rising edge of sck starting with the most significant bit. ce# must be driven low before an instruction is entered and must be driven high after the last bit of the instruction has been shifted in (except for read, read-id, and read-status- register instructions). any low-to-high transition on ce#, before receiving the last bit of an instruction bus cycle, will terminate the instruction in progress and return the device to standby mode. instruction commands (op code), addresses, and data are all input from the most significant bit (msb) first. table 8: device operation instructions for sst25wf512 and SST25WF010 instruction description op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most signi ficant bit of each density can be v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory 0000 0011b (03h) 3 0 1 to 20 mhz high-speed read read memory at higher speed 0000 1011b (0bh) 3 1 1 to 40 mhz 4 kbyte sector- erase 3 3. 4 kbyte sector-erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3 0 0 32 kbyte block- erase 4 4. 32 kbyte block-erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. erase 32 kbyte block of memory array 0101 0010b (52h) 3 0 0 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 byte-program to program one data byte 0000 0010b (02h) 3 0 1 aai-word-program 5 5. to continue programming to the next sequential address location, enter the 8-bit command, adh, followed by 2 bytes of data to be programmed. data byte 0 will be programmed into the initial address [a 23 -a 1 ] with a 0 =0, data byte 1 will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. auto address increment programming 1010 1101b (adh) 3 0 2 to rdsr 6 6. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. read-status-register 0000 0101b (05h) 0 0 1 to ewsr enable-write-status-register 0110 0000b (50h) 0 0 0 wrsr 7 7. this command is for backward compatibility to sst 25vf/lf series, user should use wrsr for new designs write-status-register 0000 0001b (01h) 0 0 1 wren write-enable 0000 0110b (06h) 0 0 0 wrdi write-disable 0000 0100b (04h) 0 0 0 rdid 8 8. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufacturer?s id and device id output stream is continuous until te rminated by a low-to-high transition on ce#. read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to ebsy enable so to output ry/by# status during aai programming 0111 000b (70h) 0 0 0 dbsy disable so to output ry/by# status during aai programming 1000 0000b (80h) 0 0 0 jedec-id jedec id read 1001 1111b (9fh) 0 0 3 to ehld enable hold# pin functionality of the rst#/hold# pin 1010 1010b (aah) 0 0 0 t8.0 1328
10 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 table 9: device operation instructions for sst25wf020 instruction description op code cycle 1 1. one bus cycle is eight clock periods. address cycle(s) 2 2. address bits above the most signi ficant bit of each density can be v il or v ih . dummy cycle(s) data cycle(s) maximum frequency read read memory 0000 0011b (03h) 3 0 1 to 20 mhz high-speed read read memory at higher speed 0000 1011b (0bh) 3 1 1 to 40 mhz 4 kbyte sector- erase 3 3. 4 kbyte sector-erase addresses: use a ms -a 12, remaining addresses are don?t care but must be set either at v il or v ih. erase 4 kbyte of memory array 0010 0000b (20h) 3 0 0 32 kbyte block- erase 4 4. 32 kbyte block-erase addresses: use a ms -a 15, remaining addresses are don?t care but must be set either at v il or v ih. erase 32 kbyte block of memory array 0101 0010b (52h) 3 0 0 64 kbyte block- erase 5 5. 64 kbyte block-erase addresses: use a ms -a 16, remaining addresses are don?t care but must be set either at v il or v ih. erase 64 kbyte block of memory array 1101 1000b (d8h) 3 0 0 chip-erase erase full memory array 0110 0000b (60h) or 1100 0111b (c7h) 000 byte-program to program one data byte 0000 0010b (02h) 3 0 1 aai-word-program 6 6. to continue programming to the next sequential address location, enter the 8-bit command, adh, followed by 2 bytes of data to be programmed. data byte 0 will be programmed into the initial address [a 23 -a 1 ] with a 0 =0, data byte 1 will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. auto address increment programming 1010 1101b (adh) 3 0 2 to rdsr 7 7. the read-status-register is continuous with ongoing clock cycles until terminated by a low to high transition on ce#. read-status-register 0000 0101b (05h) 0 0 1 to ewsr enable-write-status-register 0110 0000b (50h) 0 0 0 wrsr 8 8. this command is for backward compatibility to sst 25vf/lf series, user should use wrsr for new designs. write-status-register 0000 0001b (01h) 0 0 1 wren write-enable 0000 0110b (06h) 0 0 0 wrdi write-disable 0000 0100b (04h) 0 0 0 rdid 9 9. manufacturer?s id is read with a 0 =0, and device id is read with a 0 =1. all other address bits are 00h. the manufacturer?s id and device id output stream is continuous until te rminated by a low-to-high transition on ce#. read-id 1001 0000b (90h) or 1010 1011b (abh) 301 to ebsy enable so to output ry/by# status during aai programming 0111 000b (70h) 0 0 0 dbsy disable so to output ry/by# status during aai programming 1000 0000b (80h) 0 0 0 jedec-id jedec id read 1001 1111b (9fh) 0 0 3 to ehld enable hold# pin functionality of the rst#/hold# pin 1010 1010b (aah) 0 0 0 t9.0 1328
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 11 ?2006 silicon storage technology, inc. s71328-00-000 11/06 read (20 mhz) the read instruction, 03h, supports up to 20 mhz read. the device outputs a data stream starting from the speci- fied address location. the data stream is continuous through all addresses until terminated by a low-to-high tran- sition on ce#. the internal address pointer automatically increments until the highest memory address is reached. once the highest memory address is reached, the address pointer automatically increments to the beginning (wrap- around) of the address space. for example, for 2 mbit den- sity, once the data from the address location 3ffffh is read, the next output is from address location 000000h. the read instruction is initiate d by executing an 8-bit com- mand, 03h, followed by address bits a 23 -a 0 . ce# must remain active low for the duration of the read cycle. see figure 6 for the read sequence. figure 6: read sequence high-speed-read (40 mhz) the high-speed-read instruction supporting up to 40 mhz read is initiated by executing an 8-bit command, 0bh, fol- lowed by address bits [a 23 -a 0 ] and a dummy byte. ce# must remain active low for the duration of the high-speed- read cycle. see figure 7 for the high-speed-read sequence. following a dummy cycle, the high-speed-read instruc- tion outputs the data starting from the specified address location. the data output stream is continuous through all addresses until terminated by a low-to-high transition on ce#. the internal address po inter will automatically incre- ment until the highest memory address is reached. once the highest memory address is reached, the address pointer will automatically incr ement to the beginning (wrap- around) of the address space. for example, for 2 mbit den- sity, once the data from address location 3ffffh is read, the next output will be from address location 000000h. figure 7: high-speed-read sequence 1328 fx6.0 ce# so si sck add. 012345678 add. add. 03 high impedance 15 16 23 24 31 32 39 40 70 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 d out msb msb msb mode 0 mode 3 d out d out d out d out 1328 f07.0 ce# so si sck add. 012345678 add. add. 0b high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 64 n+2 n+3 n+4 n n+1 x msb mode 0 mode 3 d out d out d out d out 80 71 72 d out
12 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 byte-program the page-program instruction programs the bits in the selected byte to the desired data. the selected byte must be in the erased state (ffh) when initiating a program operation. a byte-program instruction applied to a pro- tected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the page-program instruction. the byte- program instruction is initiated by executing an 8-bit com- mand, 02h, followed by address bits [a 23 -a 0 ]. following the address, the data is input in order from msb (bit 7) to lsb (bit 0). ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t bp for the completion of the internal self-timed byte-program operation. see figure 8 for the page-program sequence. figure 8: byte-program sequence 1328 f08.0 ce# so si sck add. 012345678 add. add. d in 02 high impedance 15 16 23 24 31 32 39 msb lsb mode 3 mode 0
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 13 ?2006 silicon storage technology, inc. s71328-00-000 11/06 auto address increment (aai) word-program the aai program instruction allo ws multiple bytes of data to be programmed without re-issuing the next sequential address location. this feature decreases total program- ming time when multiple bytes or entire memory array is to be programmed. an aai word program instruction pointing to a protected memory area will be ignored. the selected address range must be in the erased state (ffh) when ini- tiating an aai word program operation. while within aai word programming sequence, the only valid instructions are aai word (adh), rdsr (0 5h), or wrdi (04h). users have three options to determine the completion of each aai word program cycle: hardware detection by reading the serial output, software detection by polling the busy bit in the software status register or wait t bp. refer to end- of-write detection section for details. prior to any write operation, the write-enable (wren) instruction must be executed. the aai word program instruction is initiated by executing an 8-bit command, adh, followed by address bits [a 23 -a 0 ]. following the addresses, two bytes of data is input sequentially, each one from msb (bit 7) to lsb (bit 0). the first byte of data (d0) will be programmed into the initial address [a 23 -a 1 ] with a 0 = 0, the second byte of data (d1) will be programmed into the initial address [a 23 -a 1 ] with a 0 = 1. ce# must be driven high before the aai word program instruction is executed. the user must check the busy status before entering the next valid command. once the device indicates it is no longer busy, data for the next two sequential addresses may be programmed and so on. when the last desired byte had been entered, check the busy status using the hardware method or the rdsr instruction and execute the write-disable (wrdi) instruct ion, 04h, to terminate aai. check the busy status after wrdi to determine if the device is ready for any command. see figures 11 and 12 for aai word programming sequence. there is no wrap mode during aai programming; once the highest unprotected memory address is reached, the device will exit aai operatio n and reset the write-enable- latch bit (wel = 0) and the aai bit (aai = 0). end-of-write detection there are three methods to determine completion of a pro- gram cycle during aai word programming: hardware detection by reading the serial output, software detection by polling the busy bit in the software status register or wait t bp . hardware end-of-write detection the hardware end-of-write detection method eliminates the overhead of polling the busy bit in the software status register during an aai word program operation. the 8-bit command, 70h, configures the serial output (so) pin to indicate flash busy status during aai word programming, as shown in figure 9. the 8-bit command, 70h, must be executed prior to executing an aai word-program instruc- tion. once an internal programming operation begins, asserting ce# will immediately drive the status of the inter- nal flash status on the so pin. a ?0? indicates the device is busy and a ?1? indicates the device is ready for the next instruction. de-asserting ce# will return the so pin to tri- state. the 8-bit command, 80h, disables the serial output (so) pin to output busy status during aai-word-program opera- tion and re-configures so as an output pin. once so is an output pin, allows the use of rdsr instruction for polling during aai word programming; and software status reg- ister data outputs through the so pin. this is shown in fig- ure 10. figure 9: enable so as hardware ry/by# during aai programming figure 10: disable so as hardware ry/by# during aai programming ce# so si sck 01234567 06 high impedance mode 0 mode 3 1328 f09.0 msb ce# so si sck 01234567 80 high impedance mode 0 mode 3 1328 f10.0 msb
14 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 figure 11: auto address increment (aai) word program sequence with hardware end-of-write detection figure 12: auto address increment (aai) word program sequence with software end-of-write detection 08 32 24 48 16 24 0 40 0 8 8 8 16 0 8 16 24 0 0 8 816 ce# si sck a aa ad d0 ad so d out 1328 f11.1 d1 d2 d3 ad d n-1 d n wrdi rdsr last 2 data bytes wdri to exit aai mode output status register data check for flash busy status to load next valid command load aai command, address, 2 bytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming w ren d out 08 32 24 48 16 24 0 40 0 8 8 8 16 0 8 16 24 0 0 8 816 ce# si sck a aa ad d0 ad so d out 1328 f12.0 d1 d2 d3 ad d n-1 d n wrdi rdsr last 2 data bytes wdri to exit aai mode output status register data check for flash busy status to load next valid command load aai command, address, 2 bytes data note: 1. valid commands during aai programming: aai command or wrdi command 2. user must configure the so pin to output flash busy status during aai programming w ren
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 15 ?2006 silicon storage technology, inc. s71328-00-000 11/06 sector-erase the sector-erase instruction clears all bits in the selected 4 kbyte sector to ffh. a sector-erase instruction applied to a protected memory area will be ignored. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of any command sequence. the sector-erase instruction is initiated by executing an 8-bit command, 20h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 12 ] (a ms =most significant address) are used to determine the sector address (sa x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status regis- ter or wait t se for the completion of the internal self-timed sector-erase cycle. see figure 13 for the sector-erase sequence. figure 13: sector-erase sequence 32-kbyte block-erase the block-erase instruction clears all bits in the selected 32 kbyte block to ffh. a block-erase instruction applied to a protected memory area is ignored. prior to any write oper- ation, the write-enable (wren) instruction must be exe- cuted. ce# must remain active low for the duration of any command sequence. the block-erase instruction is initi- ated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 15 ] (a ms =most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t be for the completion of the internal self-timed block-erase. see fig- ures 14 and 15 for the block-erase sequences. figure 14: 32-kbyte block-erase sequence ce# so si sck add. 012345678 add. add. 20 high impedance 15 16 23 24 31 mode 0 mode 3 1326 f13.0 msb msb ce# so si sck addr 012345678 addr addr 52 high impedance 15 16 23 24 31 mode 0 mode 3 1328 f14.0 msb msb
16 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 64-kbyte block-erase for sst25wf020 the block-erase instruction clears all bits in the selected 64 kbyte block to ffh. a block-erase instruction applied to a protected memory area is ignored. prior to any write oper- ation, the write-enable (wren) instruction must be exe- cuted. ce# must remain active low for the duration of any command sequence. the block-erase instruction is initi- ated by executing an 8-bit command, 52h, followed by address bits [a 23 -a 0 ]. address bits [a ms -a 16 ] (a ms =most significant address) are used to determine block address (ba x ), remaining address bits can be v il or v ih. ce# must be driven high before the instruction is executed. poll the busy bit in the software status register or wait t be for the completion of the internal self-timed block-erase. see fig- ures 14 and 15 for the block-erase sequences. figure 15: 64-kbyte dual-block-erase sequence chip-erase the chip-erase instruction clear s all bits in the device to ffh. a chip-erase instruction is ignored if any of the mem- ory area is protected. prior to any write operation, the write-enable (wren) instruction must be executed. ce# must remain active low for the duration of the chip-erase instruction sequence. the chip-erase instruction is initiated by executing an 8-bit command, 60h or c7h. ce# must be driven high before the instruction is executed. the user may poll the busy bit in the software status register or wait t ce for the completion of the internal self-timed chip-erase cycle. see figure 16 for the chip-erase sequence. figure 16: chip-erase sequence ce# so si sck addr 012345678 addr addr d8 high impedance 15 16 23 24 31 mode 0 mode 3 1328 f15.0 msb msb ce# so si sck 01234567 60 or c7 high impedance mode 0 mode 3 1328 f16.0 msb
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 17 ?2006 silicon storage technology, inc. s71328-00-000 11/06 read-status-register (rdsr) the read-status-register (rdsr) instruction allows read- ing of the status register. the status register may be read at any time even during a write (program/erase) operation. when a write operation is in progress, the busy bit may be checked before sending any new commands to assure that the new commands are properly received by the device. ce# must be driven low before the rdsr instruction is entered and remain low until the status data is read. read- status-register is continu ous with ongoing clock cycles until it is terminated by a low to high transition of the ce#. see figure 17 for the rdsr instruction sequence. figure 17: read-status-register (rdsr) sequence write-enable (wren) the write-enable (wren) instruction sets the write- enable-latch bit in the status register to 1 allowing write operations to occur. the wren instruction must be exe- cuted prior to any write (program/erase) operation. the wren instruction may also be used to allow execution of the write-status-register (wrsr) instruction; however, the write-enable-latch bit in the status register will be cleared upon the rising edge ce# of the wrsr instruction. ce# must be driven high before the wren instruction is executed. figure 18: write enable (wren) sequence 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 1327 f17.0 mode 3 sck si so ce# bit 7 bit 6 bit 5 bit 4 bit 3 bit 2 bit 1 bit 0 05 mode 0 high impedance status register out msb msb ce# so si sck 01234567 06 high impedance mode 0 mode 3 1328 f18.0 msb
18 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 write-disable (wrdi) the write-disable (wrdi) instruction resets the write- enable-latch bit and aai to 0 disabling any new write operations from occurring. the wrdi instruction will not terminate any programming operation in progress. any pro- gram operation in progress may continue up to t bp after executing the wrdi instruction. ce# must be driven high before the wrdi instruction is executed. figure 19: write disable (wrdi) sequence enable-write-stat us-register (ewsr) the enable-write-status-register (ewsr) instruction arms the write-status-register (wrsr) instruction and opens the status register for alteration. the write-status- register instruction must be executed immediately after the execution of the enable-write-status-register instruction. this two-step instruction sequence of the ewsr instruc- tion followed by the wrsr instruction works like sdp (soft- ware data protection) command structure which prevents any accidental alteration of the status register values. ce# must be driven low before the ewsr instruction is entered and must be driven high before the ewsr instruction is executed. ce# so si sck 01234567 04 high impedance mode 0 mode 3 1328 fx19.0 msb
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 19 ?2006 silicon storage technology, inc. s71328-00-000 11/06 write-status-register (wrsr) the write-status-register instruction writes new values to the bp1, bp0, and bpl bits of the status register. ce# must be driven low before the command sequence of the wrsr instruction is entered and driven high before the wrsr instruction is executed. see figure 20 for ewsr or wren and wrsr instruction sequences. executing the write-status-register instruction will be ignored when wp# is low and bpl bit is set to ?1?. when the wp# is low, the bpl bit can only be set from ?0? to ?1? to lock-down the status register, but cannot be reset from ?1? to ?0?. when wp# is high, the lock-down function of the bpl bit is disabled and the so, bpl, bp0, and bp1 bits in the status register can all be changed . as long as bpl bit is set to ?0? or wp# pin is driven high (v ih ) prior to the low-to-high transition of the ce# pin at the end of the wrsr instruc- tion, the bits in the status register can all be altered by the wrsr instruction. in this case, a single wrsr instruction can set the bpl bit to ?1? to lock down the status register as well as altering the so, bp0, and bp1 bits at the same time. see table 3 for a summary description of wp# and bpl functions. figure 20: enable-write-status-register (ewsr) or write-enable (wren) and write-status-register (wrsr) sequence enable-hold (ehld) the 8-bit command, aah, enable-hold instruction enables the hold functionality of the rst#/hold# pin. ce# must remain active low for the duration of the enable-hold instruction sequence. the enable-hold instruction is initi- ated by executing an 8-bit command, aah. ce# must be driven high before the instruction is executed. see figure 21 for the enable-hold instruction sequence. figure 21: enable-hold sequence 1328 f20.0 mode 3 high impedance mode 0 status register in 76543210 msb msb msb 01 mode 3 sck si so ce# mode 0 50 or 06 0 1 2 3 4 5 6 7 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 ce# so si sck 01234567 aa high impedance mode 0 mode 3 1328 f21.0 msb
20 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 read-id the read-id instruction identifies the manufacturer as sst and the device as sst25wf512/010/020. use the read- id instruction to identify sst device when using multiple manufacturers in the same socket. the device information is read by executing an 8-bit com- mand, 90h or abh, followed by address bits [a 23 -a 0 ]. fol- lowing the read-id instruction, the manufacturer?s id is located in address 000000h and the device id is located in address 000001h. once the device is in read-id mode, the manufacturer?s and devi ce id output data toggles between address 000000h and 000001h until terminated by a low to high transition on ce#. figure 22: read-id sequence table 10: product identification address data manufacturer?s id 000000h bfh device id sst25wf512 SST25WF010 sst25wf020 00001h 00001h 00001h 01h 02h 03h t10.1328 1328 f22.0 ce# so si sck 00 012345678 00 add 90 or ab high impedance 15 16 23 24 31 32 39 40 47 48 55 56 63 bf device id bf device id note: 1. the manufacturer's and device id output stream is continuous until terminated by a low to high transition on ce#. 2. 00h will output the manfacturer's id first and 01h will output device id first before toggling between the two. high impedance mode 3 mode 0 msb msb msb
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 21 ?2006 silicon storage technology, inc. s71328-00-000 11/06 jedec read-id the jedec read-id instruction identifies the device as sst25wf512/010/020 and the manufacturer as sst. the device information can be read from executing the 8-bit command, 9fh. following the jedec read-id instruction, the 8-bit manufacturer?s id, bfh, is output from the device. after that, a 16-bit device id is shifted out on the so pin. the device id is assigned by the manufacturer and con- tains the type of memory in the first byte and the memory capacity of the device in the second byte. see figure 23 for the instruction sequence. the jedec read id instruction is terminated by a low to high transition on ce# at any time during data output. figure 23: jedec read-id sequence table 11: jedec read-id da ta-out for sst25wf512 manufacturer?s id (byte 1) device id memory type (byte 2) memory capacity (byte 3) bfh 25h 01h t11.0 1328 table 12: jedec read-id da ta-out for SST25WF010 manufacturer?s id (byte 1) device id memory type (byte 2) memory capacity (byte 3) bfh 25h 02h t12.0 1328 table 13: jedec read-id da ta-out for sst25wf020 manufacturer?s id (byte 1) device id memory type (byte 2) memory capacity (byte 3) bfh 25h 03h t13.0 1328 25 01/02/03 note: 1. 01 indicates 25wf512, 02 indicates 25wf010, 03 indicates 25wf020 1328 f23.0 ce# so si sck 012345678 high impedance 15 16 14 28 29 30 31 bf mode 3 mode 0 msb msb 9 10111213 1718 32 34 9f 19 20 21 22 23 33 24 25 26 27
22 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 electrical specifications dc characteristics absolute maximum stress ratings (applied conditions greater than t hose listed under ?absolute maximum stress ratings? may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these conditions or conditions greater t han those defined in the operational sections of this data sheet is not implied. exposu re to absolute maximum stress rating co nditions may affect device reliability.) temperature under bias . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -55c to +125c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -65c to +150c d. c. voltage on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0. 5v to v dd +0.5v transient voltage (<20 ns) on any pin to ground potential . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -2.0v to v dd +2.0v package power dissipation capability (t a = 25c) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.0w surface mount solder reflow temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 260c for 10 seconds output short circuit current 1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50 ma 1. output shorted for no more than one second. no more than one output shorted at a time. o perating r ange range ambient temp v dd commercial 0c to +70c 1.65-1.95v industrial -40c to +85c 1.65-1.95v ac c onditions of t est input rise/fall time . . . . . . . . . . . . . . . 5 ns output load . . . . . . . . . . . . . . . . . . . . . c l = 30 pf table 14: dc operating characteristics symbol parameter limits test conditions min max units i ddr read current 15 ma ce#=0.1 v dd /0.9 v dd @20 mhz, so=open i ddr2 read current 18 ma ce#=0.1 v dd /0.9v dd @40 mhz, so=open i ddw program and erase current 15 ma ce#=v dd i sb standby current 10 a ce#=v dd , v in =v dd or v ss i li input leakage current 10 a v in =gnd to v dd , v dd =v dd max i lo output leakage current 10 a v out =gnd to v dd , v dd =v dd max v il input low voltage 0.3 v v dd =v dd min v ih input high voltage 0.7 v dd vv dd =v dd max v ol output low voltage 0.2 v i ol =100 a, v dd =v dd min v oh output high voltage v dd -0.2 v i oh =-100 a, v dd =v dd min t14.0 1328 table 15: capacitance (t a = 25c, f=1 mhz, other pins open) parameter description test condition maximum c out 1 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. output pin capacitance v out = 0v 12 pf c in 1 input capacitance v in = 0v 6 pf t15.0 1328
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 23 ?2006 silicon storage technology, inc. s71328-00-000 11/06 ac characteristics table 16: reliability characteristics symbol parameter minimum spec ification units test method n end 1 endurance 10,000 cycles jedec standard a117 t dr 1 data retention 100 years jedec standard a103 i lt h 1 latch up 100 + i dd ma jedec standard 78 t16.0 1328 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. table 17: ac operating characteristics limits - 20 mhz limits - 40 mhz symbol parameter min max min max units f clk 1 1. maximum clock frequency for read instruction, 03h, is 20 mhz serial clock frequency 20 40 mhz t sckh serial clock high time 20 11 ns t sckl serial clock low time 20 11 ns t sckr serial clock rise time 5 5 ns t sckf serial clock fall time 5 5 ns t ces 2 2. relative to sck ce# active setup time 20 8 ns t ceh 2 ce# active hold time 20 8 ns t chs 2 ce# not active setup time 10 10 ns t chh 2 ce# not active hold time 10 10 ns t cph ce# high time 100 100 ns t chz ce# high to high-z output 20 19 ns t clz sck low to low-z output 0 0 ns t ds data in setup time 5 2 ns t dh data in hold time 5 5 ns t hls hold# low setup time 10 8 ns t hhs hold# high setup time 10 8 ns t hlh hold# low hold time 15 12 ns t hhh hold# high hold time 10 10 ns t hz hold# low to high-z output 20 20 ns t lz hold# high to low-z output 20 20 ns t oh output hold from sck change 0 0 ns t v output valid from sck 20 9 ns t se sector-erase 75 75 ms t be block-erase 75 75 ms t sce chip-erase 150 150 ms t bp 3 3. aai-word program tbp maximum specification is also at 60 s maximum time byte-program 60 60 s t17.1 1328
24 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 figure 24: serial input timing diagram figure 25: serial output timing diagram table 18: recommended system power-up timings symbol parameter minimum units t pu-read 1 v dd min to read operation 100 s t pu-write 1 v dd min to write operation 100 s t18.0 1328 1. this parameter is measured only for init ial qualification and after a design or proc ess change that could affect this paramet er. high-z high-z ce# so si sck msb lsb t ds t dh t chh t ces t ceh t chs t sckr t sckf t cph 1326 f24.0 1328 f25.0 ce# si so sck msb t clz t v t sckh t chz t oh t sckl lsb
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 25 ?2006 silicon storage technology, inc. s71328-00-000 11/06 figure 26: hold timing diagram figure 27: power-up timing diagram t hz t lz t hhh t hls t hlh t hhs 1328 f26.0 hold# ce# sck so si time v dd min v dd max v dd device fully accessible t pu-read t pu-write chip selection is not allowed. commands may not be accepted or properly interpreted by the device. 1326 f27.0
26 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 figure 28: ac input/output reference waveforms 1326 f28.0 reference points output input? v ht v lt v ht v lt v iht v ilt ac test inputs are driven at v iht (0.9v dd ) for a logic ?1? and v ilt (0.1v dd ) for a logic ?0?. measurement reference points for inputs and outputs are v ht (0.6v dd ) and v lt (0.4v dd ). input rise and fall times (10% ? 90%) are <5 ns. note: v ht - v high te s t v lt - v low te s t v iht - v input high test v ilt - v input low test
advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 27 ?2006 silicon storage technology, inc. s71328-00-000 11/06 product ordering information valid combinations for sst25wf512 sst25wf512-40-4i-saf valid combinations for SST25WF010 SST25WF010-40-4i-saf valid combinations for sst25wf020 sst25wf020-40-4i-saf note: valid combinations are those products in mass producti on or will be in mass production. consult your sst sales representative to confirm availability of valid combinat ions and to determine availability of new combinations. sst 25 wf xxx - 40 - 4i - sa f xx x xxxx -xx -xx -xx x environmental attribute f 1 = non-pb / non-sn contact (lead) finish: package modifier a = 8 leads or bumps package type s = soic 150 mil body width temperature range i = industrial = -40c to +85c minimum endurance 4 = 10,000 cycles operating frequency 40 = 40 mhz device density 512 = 512 kbit 010 = 1 mbit 020 = 2 mbit voltage w= 1.65-1.95v product series 25 = serial peripheral interface flash memory 1. environmental suffix ?f? denotes non-pb/non-sn solder. sst non-pb/non-sn solder devi ces are ?rohs compliant?.
28 advance information 512 kbit / 1 mbit / 2 mbit 1.8v spi serial flash sst25wf512 / SST25WF010 / sst25wf020 ?2006 silicon storage technology, inc. s71328-00-000 11/06 packaging diagrams figure 29: 8-lead small outlin e integrated circuit (soic) sst package code: sa table 19: revision history number description date 00 ? initial release of data sheet nov 2006 08-soic-5x6-sa-8 note: 1. complies with jedec publication 95 ms-012 aa dimensions, although some dimensions may be more stringent. 2. all linear dimensions are in millimeters (max/min). 3. coplanarity: 0.1 mm 4. maximum allowable mold flash is 0.15 mm at the package ends and 0.25 mm between leads. top view side view end view 5.0 4.8 6.20 5.80 4.00 3.80 pin #1 identifier 0.51 0.33 1.27 bsc 0.25 0.10 1.75 1.35 7 4 places 0.25 0.19 1.27 0.40 45 7 4 places 0 8 1mm silicon storage technology, inc. ? 1171 sonora court ? sunnyvale, ca 94086 ? telephone 408-735-9110 ? fax 408-735-9036 www.superflash.com or www.sst.com

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